1. Field of the Invention
The present invention relates to a clock gating circuit having a clock gating function for stopping supply of a clock signal according to an operating state, and more particularly, to a failure detection technique.
2. Description of Related Art
Along with the recent increase in scale of large-scale integration (LSI), a technique for reducing power consumption in LSI design has been required. A clock gating technique is known as an example of the technique for reducing power consumption. The clock gating technique is used for stopping supply of a clock signal to inactive circuits during execution of an application.
In the recent LSI design, automatic layout tools are generally used. When the clock gating technique is employed in the LSI design, a clock gating circuit is usually prepared in advance as a macro cell.
Further, in an LSI manufacturing process, a test for detecting a failure in a circuit is carried out. A scan design technique is known as an example of a design technique for improving the failure detection accuracy of the test.
A circuit shown in FIG. 6 will be described as an example of the clock gating circuit to which the scan 5 design technique is applied. Note that the clock gating circuit switches ON/OFF (propagation/stop) of an output clock signal in response to a control signal (clock enable signal). In the case of the clock gating circuit of the related art, however, a glitch may occur in the output clock signal, depending on the timing of switching the clock enable signal. For this reason, a clock gating circuit 100 shown in FIG. 6 includes a latch circuit 104 for preventing a glitch from occurring.
The clock gating circuit 100 includes an OR gate (hereinafter referred to simply as “OR”) 102, an AND gate (hereinafter referred to simply as “AND”) 103, and the latch 104. A test enable signal TEN is input to one input terminal of the OR 102 through an external input terminal 105. A clock enable signal CEN is input to the other input terminal of the OR 102 through an external input terminal 106. A signal output from the OR 102 is input to an input terminal LD of the latch 104. A signal output from an output terminal LQ of the latch 104 is input to one input terminal of the AND 103. A clock signal CLK is input to the other input terminal of the AND 103 and to an input terminal LG of the latch 104 through an external input terminal 107. A signal output from the AND 103 is supplied to an external output terminal 108 as a gated clock signal GCLK.
In the case of the circuit shown in FIG. 6, mode switching is made between a scan test mode and a normal operation mode based on the TEN signal. During a scan test, for example, the TEN signal is fixed at the level of “1”. Thus, the circuit shown in FIG. 6 directly propagates the CLK signal and outputs it as the GCLK signal. In this case, however, the output signal of the latch 104 is fixed at the level of “1”. This makes it impossible to detect a failure in the output signal of the latch 104. In other words, the failure detection accuracy is degraded.
A solution for this problem is proposed in “Power Compiler User Guide Ver. Y-2006.06”, June 2006, p. 208, provided by Synopsys, Inc. FIG. 7 shows a clock gating circuit and an observation circuit which are disclosed in “Power Compiler User Guide Ver. Y-2006.06”, June 2006, p. 208, provided by Synopsys, Inc.
The circuit shown in FIG. 7 has a circuit configuration capable of detecting a failure in the output signal of the latch in the clock gating circuit. The circuit shown in FIG. 7 includes a clock gating circuit 130 as well as an observation circuit 140 including an observation flip-flop 147.
The clock gating circuit 130 includes an OR 132, an AND 133, and a latch 131. The clock enable signal is input to an input terminal LD of the latch 131. A signal output from an output terminal LQ of the latch 131 is input to one input terminal of the OR 132. The test enable signal TEN is input to the other input terminal of the OR 132 through an external input terminal 118. A signal output from the OR 132 is input to one input terminal of the AND 133. The clock signal CLK is input to the other input terminal of the AND 133 and to an input terminal LG of the latch 131 through an external input terminal 114. The AND 133 outputs the gated clock signal GCLK to a clock input terminal of the flip-flop 113 provided at the subsequent stage.
The observation circuit 140 includes three NANDs 141, 142, and 143, two EXOR gates (hereinafter referred to simply as “EXORs”) 144 and 145, an AND 146, and the observation flip-flop 147.
The TEN signal is input to one input terminal of each of the NANDs 141, 142, and 143. A signal 119 output from the clock gating circuit 130 (the signal is hereinafter referred to simply as “ENLa signal”) is input to the other input terminal of the NAND 143. Note that the ENLa signal 119 is a signal output from the output terminal LQ of the latch 131 in the clock gating circuit 130. Further, in a similar manner as in the NAND 143, an ENLc signal 121 and an ENLb signal 120, which are output from another clock gating circuit (not shown), are input to the other input terminals of the NANDs 141 and 142, respectively.
The signals output from the NANDs 142 and 143 are respectively input to input terminals of the EXOR 144. A signal output from the EXOR 144 is input to one input terminal of the EXOR 145. A signal output from the NAND 141 is input to the other input terminal of the EXOR 145. A signal output from the EXOR 145 is input to an input terminal D of the observation flip-flop 147.
The CLK signal is input to one input terminal of the AND 146. The TEN signal is input to the other input terminal of the AND 146. A signal output from the AND 146 is input to a clock input terminal of the observation flip-flop 147. The observation flip-flop 147 outputs a scan output signal SOT to an external output terminal 122.
Further, FIG. 7 shows flip-flops 111 and 113 as examples of peripheral circuits connected at the preceding and subsequent stages of the clock gating circuit 130. The CLK signal is input to a clock input terminal of the flip-flop 111. A signal output from an output terminal Q of the flip-flop 111 is input to the input terminal LD of the latch 131 through a control logic 112.
Further, the GCLK signal output from the AND 133 is input to the clock input terminal of the flip-flop 113. An output signal 117 output from another circuit is input to an input terminal D of the flip-flop 113. The flip-flop 113 outputs an output signal 116. Note that the clock gating circuit controls the supply of the clock signal by the flip-flop 113.
In this case, the TEN signal is input to the other input terminal of the AND 133 not through the latch 131. Accordingly, the clock gating circuit 130 shown in FIG. 7 has a configuration capable of detecting a failure in the output signal of the latch 131 since the output signal of the latch 131 is not fixed at one voltage level by the TEN signal. Further, the observation circuit 140 shown in FIG. 7 can detect a failure in three clock gating circuits to thereby prevent an increase in circuit size.